1. Field of the Invention
This invention relates to semiconductor fabrication and more particularly to an integrated circuit which employs a multilevel interconnect structure having thickened conductors in regions of dense interconnect. The thickened conductors of enhanced cross-sectional area have potential for carrying larger amounts of current commensurate with wide conductors. However, minimum spacing requirements available in regions of dense interconnect prevent use of wide conductors.
2. Description of the Relevant Art
An integrated circuit includes numerous conductors extending across the topography of a monolithic substrate. A set of interconnect lines (or conductors) which serve to electrically connect two or more components within a system is generally referred to as a "bus". A collection of voltage levels are forwarded across the conductors to allow proper operation of the components. For example, a microprocessor is connected to memories and input/output devices by certain bus structures. There are numerous types of busses which are classified according to their operation. Examples of well-known types of busses include address busses, data busses and control busses.
Conductors within a bus generally extend partially parallel to each other across the semiconductor topography. The conductors are isolated from each other and from underlying conductive elements by a dielectric, a suitable dielectric being, for example, silicon dioxide ("oxide"). Conductors are thereby lithography patterned across the semiconductor topography, wherein the topography comprises a substrate with a dielectric placed thereon. Conductors are made from an electrically conductive material, a suitable material includes Al, Ti, Ta, W, Mo, polysilicon, or a combination thereof. The substrate includes any type of material which can retain dopant ions and the isolated conductivity regions brought about by those ions. Typically, the substrate is a silicon-based material which receives p-type or n-type ions. Generally speaking, interconnect lines (or conductors) are fashioned upon the topography and dielectrically spaced above an underlying conductor or substrate. Each conductor is dielectrically spaced from other conductors within the same level of conductors (i.e., substantially coplanar conductors) by a defined lateral distance. Each conductor is designed to carry a certain amount of current, based on the desired design and application. As a conductor carries current, a migration of conductive material occurs from one part of the conductor to another. Migration of material, i.e., electromigration, causes localized thinning of the conductor leading to a resistance increase. The useful lifetime of a conductor thereby decreases with decreasing conductor cross-sectional area.
Electromigration causes a reliability issue. Design results are used to calculate a minimum width of the conductor based upon current requirement through the conductor. In order to maintain relatively small conductor widths (i.e., to maintain a small die size), it would be desirable to derive a technique for reworking a conductor to enhance its current-carrying capability. The importance of rework is particularly acute if rework can be selectively performed on certain conductors but not all conductors within a die. Thus, in many design layouts, there may exist conductors which have less than a minimum specified width to pass electromigration specification. The normal procedure for increasing width of the conductor is to move neighboring conductors to allow for increase in conductor width, increase die size to allow for increase in conductor width, or jeopardize minimum conductor spacing adjacent to the widened conductor. These re-work scenarios are intolerable in most instances.
If a conductor cannot carry sufficient current for a desired application, the conductor is generally reconfigured in a manner involving a circuit revision or "design fix". In order to carry larger amounts of current, the reconfigured conductor can be made wider (i.e., wider in a lateral direction parallel to the semiconductor topography) than the other conductors. A negative consequence of widening a conductor is the encroachment of that conductor toward laterally spaced (neighboring) conductors. If adjacent conductors were originally configured a minimum space apart, one conductor cannot be made wider if the minimum spacing is violated. Thus, widening a conductor typically requires moving minimum-spaced, adjacent conductors away from the widened conductor. This reconfiguration may in certain instances be extremely burdensome and may impact the placement of numerous conductors arranged across the semiconductor die.
It would therefore be desirable to derive a technique for reworking a conductor to enhance its current-carrying capacity without having to reconfigure or move any other conductor arranged adjacent the enhanced conductor. The enhanced conductor must be one which can be readily reworked with minimal impact upon photolithography steps used in forming that conductor (or any other conductor upon the die). A technique must therefore be derived which can reconfigure select conductors in densely spaced areas without having to modify laterally adjacent conductors. This technique would be advantageous in circuit rework operations and would reduce the time required to produce circuit revisions. Enhancing a conductor's current-carrying capability without jeopardizing minimum conductor spacing would not only achieve current drive specifications but would do so without sacrificing propagation delay or cross-coupling noise.